中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装

• 综述 •    下一篇

混合键合界面接触电阻及界面热阻研究进展

吴艺雄1,杜韵辉1,陶泽明1,钟毅1,于大全1,2   

  1. 1. 厦门大学电子科学与技术学院,福建 厦门  361005;2. 厦门云天半导体科技有限公司,福建 厦门  361013
  • 收稿日期:2025-01-02 修回日期:2025-01-16 出版日期:2025-02-11 发布日期:2025-02-11
  • 通讯作者: 钟毅
  • 基金资助:
    国家自然科学基金(62474146、62104206);中央高校基本科研业务费专项资金(20720220072)

Research Progress on Interfacial Contact Resistance and Thermal Boundary Resistance of Hybrid Bonding

WU Yixiong1, DU Yunhui1, TAO Zeming1, ZHONG Yi1, YU Daquan1,2   

  1. 1. School of Electronic Science and Engineering, Xiamen University, Xiamen, 361005, China; 2. Xiamen Sky Semiconductor Technology Co., Ltd., Xiamen 361013, China
  • Received:2025-01-02 Revised:2025-01-16 Online:2025-02-11 Published:2025-02-11

摘要: 随着半导体技术向更高集成度和性能要求发展,混合键合技术作为一种先进封装方法,在集成电路领域中展现了巨大的应用潜力。综述了混合键合界面接触电阻和界面热阻的研究进展,探讨了混合键合在三维集成芯片中的应用,重点分析了其在降低电阻、优化热阻方面的技术突破。总结了影响界面电阻和热阻的关键因素,并评估了不同工艺对性能的影响。探讨了界面处理、表面粗糙度、清洗时间和退火工艺等因素对接触电阻的显著影响,分析了界面材料和多物理场耦合效应在优化热阻方面的重要作用。此外,细间距混合键合技术的进展推动了芯片封装密度的提升,但随着间距的缩小,界面应力和对准误差等问题仍需进一步解决。

关键词: 先进封装, 高密度互连, 界面热阻, 接触电阻, 开尔文结构

Abstract: As semiconductor technology advances towards higher levels of integration and performance, hybrid bonding technology has shown great potential in the field of integrated circuits as an advanced packaging method. This paper reviews the research progress on interface contact resistance and thermal resistance in hybrid bonding, exploring its application in 3D integrated chips, with a focus on the technological breakthroughs in reducing resistance and optimizing thermal resistance. Key factors influencing interface resistance and thermal resistance are summarized, and the impact of various processes on performance is evaluated. Factors such as interface treatment, surface roughness, cleaning time, and annealing process have a significant impact on contact resistance, while interface materials and multiphysical coupling effects play an important role in optimizing thermal resistance. Furthermore, the advancement of fine-pitch hybrid bonding technology has driven the increase in chip packaging density, but as the pitch continues to shrink, issues such as interface stress and alignment errors still need to be further addressed.

Key words: advanced packaging, high density interconnection, thermal boundary resistance, contact resistance, kelvin structure