关键词: 封装载板, 翘曲, 热应力

Abstract: Coreless packaging substrates are widely adopted in advanced packaging due to their superior electrical properties and fine-pitch routing capabilities. However, their multilayer structure is prone to thermal stress and warpage during temperature cycling or process heating/cooling, compromising chip interconnect reliability. By constructing a finite element model of the coreless substrate and employing Taguchi experimental design methodology, the influence of substrate thickness on warpage was elucidated. Simulation and experimental design analysis indicate that top-layer solder mask thickness and L1 copper thickness exhibit significant warpage suppression effects, while the bottom-layer structure remains the primary driver of warpage. Theoretical optimal specifications derived from equivalent stiffness and thermal expansion matching mechanisms were experimentally validated, confirming the simulation model's effectiveness in predicting warpage trends. An optimization strategy was established to compensate for residual copper rate variations through asymmetric thickness design.

Key words: substrate, warpage, thermal stress