基于可布线性预测的AI模型训练及布局优化方法

doi:10.16257/j.cnki.1681-1070.2026.0064

摘要/Abstract

摘要： 目前工业界主流FPGA设计规模已超过亿门级，传统布局算法优化因为优化目标与实际布线需求无法完全一致，已无法满足用户对超大规模电路的设计需求。提出一种基于改进ResNet50的可布线性预测及布局优化方法，建立了布局参数与布线布通率的数据映射模型，并提出一种布局布线协同优化手段，利用布局参数作为可布线性预测模型的输入，以布线结果作为训练目标进行模型训练，进而通过训练好的模型指导布局优化。测试结果表明，所提方法能有效提升布通率。

关键词: 布局优化, 可布线性预测, ResNet50, FPGA

Abstract: Currently, the mainstream FPGA design scale in the industry has exceeded 100 million gates, and traditional placement algorithm optimization has been unable to meet the design needs of users for ultra-large-scale circuits because the optimization objectives cannot be completely consistent with the actual routing requirements. A placement method based on improved ResNet50 is proposed and a data mapping model between placement parameters and routing completion rate is established. Meanwhile, a collaborative optimization method for placement and routing is proposed. The placement parameters are used as the training input to the AI model, and the routing result is used as the training target for the model. The trained model is then used to optimize the placement. According to the test results, this method effectively improves routing completion rate.

Key words: placement optimization, routability prediction, ResNet50, FPGA

中图分类号:

虞健，惠峰，姜姗，谢达. 基于可布线性预测的AI模型训练及布局优化方法[J]. 电子与封装, 2026, 26(6): 060301 .

YU Jian, HUI Feng, JIANG Shan, XIE Da. AI Model Training and Placement Optimization Method Based on Routeability Prediction[J]. Electronics & Packaging, 2026, 26(6): 060301 .

参考文献

[1] BETZ V, ROSE J. FPGA routing architecture: segmentation and buffering to optimize speed and density[C]//Proceedings of the 1999 ACM/SGIDA seventh international symposium on Field programmable gate arrays, Monterey, California, USA ,1999: 59-68.
[2] BETZ V, ROSE J, MARQUARDT A. Architecture and CAD for deep-submicron FPGAS[M]. Boston: Springer US, 1999.
[3] KAHNG A B, WANG Q K. A faster implementation of APlace[C]//Proceedings of the 2006 International Symposium on Physical Design, San Jose, California, USA, 2006: 218-220.
[4] HUANG G Y, HU J B, HE Y F, et al. Machine learning for electronic design automation: A survey[J]. ACM Transactions on Design Automation of Electronic Systems (TODAES), 2021, 26(5): 1-46.
[5] LIN Y B, DHAR S, LI W X, et al. Dreamplace: deep learning toolkit-enabled GPU acceleration for modern VLSI placement[C]//Proceedings of the 56th Annual Design Automation Conference 2019, Las Vegas, NV, USA, 2019.
[6] LU Y C, PENTAPATI S, LIM S K. The law of attraction: affinity-aware placement optimization using graph neural networks[C]//Proceedings of the 2021 International Symposium on Physical Design, Virtual, Online, 2021: 7-14.
[7] LU Y C, PENTAPATI S, LIM S K. VLSI placement optimization using graph neural networks[C]// 34th Advances in Neural Information Processing Systems (NeurIPS) Workshop on ML for Systems, Virtual, Online, 2020: 6-12.
[8] GOLDIE A, MIRSHOSEINI A. Placement optimization with deep reinforcement learning[C]// International Symposium on Physical Design, Taibei, Taiwan, China, 2020: 3-7.
[9] MIRHOSEINI A, GOLDIE A, YAZGAN M, et al. Chip placement with deep reinforcement learning[EB/OL]. (2020-04-22)[2026-05-05]. https://arxiv.org/abs/2004.10746
[10] MIRHOSEINI A, GOLDIE A, YAZGAN M, et al. A graph placement methodology for fast chip design[J]. Nature, 2021, 594(7862): 207-212.
[11] CHENG R Y, YAN J C. On joint learning for solving placement and routing in chip design[C]//Neural Information Processing Systems, Virtual, Online, 2021.
[12] XIE Z Y, HUANG Y H, FANG G Q, et al. RouteNet: routability prediction for mixed-size designs using convolutional neural network[C]//2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Diego, CA, USA, 2019: 1-8.
[13] HUANG Y H, XIE Z Y, FANG G Q, et al. Routability-driven macro placement with embedded CNN-based prediction model[C]//2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019: 180-185.
[14] LIU S T, SUN Q, LIAO P Y, et al. Global placement with deep learning-enabled explicit routability optimization[C]//2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), Grenoble, France, 2021: 1821-1824.
[15] HE K M, ZHANG X Y, REN S Q, et al. Deep residual learning for image recognition[C]//2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), Las Vegas, NV, USA, 2016: 770-778.
[16] SPINDLER P, JOHANNES F M. Fast and accurate routing demand estimation for efficient routability-driven placement[C]//2007 Design, Automation & Test in Europe Conference & Exhibition, Nice, France, 2007: 1-6.
[17]虞健, 董志丹, 惠锋, 等. Quadratic布局算法力模型的建立和一种均匀展开的方法[J]. 电子与封装, 2017, 17(7): 31-35.
[18] HART P E, NILSSON N J, RAPHAEL B. A formal basis for the heuristic determination of minimum cost paths[J]. IEEE Transactions on Systems Science and Cybernetics, 1968, 4(2): 100-107.

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