电子与封装
• 封装、组装与测试 • 下一篇
华枫，张秀均，辛赟龙
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HUA Feng, ZHANG Xiujun, XIN Yunlong
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摘要： 基于JTAG协议的边界扫描技术能够进行互连测试，但目前基于非完全BS结构的SiP芯片中裸芯的互连测试研究较少。本文为解决这一问题提出了一种基于SVF和BSDL文件的测试方法。该测试方法通过包含边界扫描端口的FPGA控制不含边界扫描结构的FLASH器件，可以验证SiP芯片裸芯间的互连是否正常，并通过实际波形验证该方法的可行性。为其他非完全BS结构SiP芯片提供一种测试方法。
关键词: SIP, 边界扫描, SVF, BSDL, 互连测试
Abstract: The boundary scan technology based on the JTAG protocol can be used for interconnection testing. However, at present, there are relatively few studies on the interconnection testing of bare chips in SiP chips based on non-fully BS structure. This paper proposes a testing method based on SVF and BSDL files to address this issue. This testing method controls the FLASH device without boundary scan structure by using an FPGA that incorporates boundary scan ports. It is possible to verify whether the interconnections between the bare chips of the SiP chip are functioning properly. This method verifies the feasibility of the method through actual waveforms, and provides a testing method for other non-fully BS-structured SiP chips.
Key words: SIP, boundary scan, SVF, BSDL, interconnect test
华枫, 张秀均, 辛赟龙. 基于JTAG的非完全BS结构的SiP芯片内部互连测试[J]. 电子与封装, doi: 10.16257/j.cnki.1681-1070.2026.0066.
HUA Feng, ZHANG Xiujun, XIN Yunlong. Internal Interconnection Testing of SiP Chip with Non-Fully BS Structure Based on JTAG[J]. Electronics & Packaging, doi: 10.16257/j.cnki.1681-1070.2026.0066.
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链接本文: https://ep.org.cn/CN/10.16257/j.cnki.1681-1070.2026.0066
