中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊

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电子与封装 ›› 2025, Vol. 25 ›› Issue (5): 050102 . doi: 10.16257/j.cnki.1681-1070.2025.0074

• “面向先进封装应用的铜互连键合技术”专题 • 上一篇    下一篇

面向高密度互连的混合键合技术研究进展*

白玉斐,戚晓芸,牛帆帆,康秋实,杨佳,王晨曦   

  1. 哈尔滨工业大学材料结构精密焊接与连接全国重点实验室,哈尔滨 150001
  • 收稿日期:2024-12-30 出版日期:2025-06-04 发布日期:2025-02-17
  • 作者简介:白玉斐(2000—),女,山东济宁人,博士研究生,主要研究方向为低温晶圆键合及三维异质集成;王晨曦(1980—),男,黑龙江伊春人,博士,教授,博士生导师,主要研究方向为晶圆键合、芯片异质集成与封装、精密焊接与微纳连接、医用新材料连接等。

Research Progress of Hybrid Bonding Technology for High-Density Interconnects

BAI Yufei, QI Xiaoyun, NIU Fanfan, KANG Qiushi, YANG Jia, WANG Chenxi   

  1. StateKey Laboratory of Precision Welding & Joining of Materials and Structures, Harbin Institute of Technology,Harbin 150001, China
  • Received:2024-12-30 Online:2025-06-04 Published:2025-02-17

摘要: 在数字经济时代,人工智能、高性能计算、大数据、物联网和自动驾驶等新兴产业的迅猛发展对计算能力提出了极高的需求。然而,随着先进制程逐渐逼近物理极限,摩尔定律的发展速度显著放缓,传统的引线键合技术已难以满足数字经济对高算力芯片的需求。在此背景下,三维集成技术作为一种革命性的解决方案应运而生。混合键合作为三维集成技术的基石,通过金属层和金属层、介电层和介电层的直接键合,实现了无凸点的高密度互连。与传统键合技术相比,混合键合不仅能够实现亚微米甚至纳米级的互连间距,还显著降低了信号延迟与功耗,提升了芯片的带宽与容量,为高性能芯片的实现提供了关键支持。在后摩尔时代,混合键合被视为先进封装的核心发展方向之一,可实现窄间距、高密度、小尺寸的互连结构,满足新兴应用场景对芯片性能的苛刻要求。系统介绍了面向高密度互连的混合键合技术,重点总结了其所采用的新型金属钝化层等关键材料以及核心工艺,深入论述了混合键合技术在高带宽内存领域的应用现状及发展趋势,旨在为先进封装技术的持续创新与发展提供参考与思路。

关键词: 混合键合, 高密度互连, 三维集成, 高带宽内存

Abstract: In the era of the digital economy, the rapid advancement of emerging industries, such as artificial intelligence, high-performance computing, big data, Internet of Things, and autonomous driving, has placed an extremely high demand on computational power. However, as advanced processes approach physical limits and Moore's Law has slowed down significantly, traditional wire bonding technologies are no longer capable of meeting the computational demand of high-performance chips in the digital economy. Against this backdrop, 3D integration technology has emerged as a transformative solution. As a cornerstone of 3D integration technology, hybrid bonding enables bumpless high-density interconnections through the direct bonding of metal-to-metal layers and dielectric-to-dielectric layers. Compared with conventional bonding technology, hybrid bonding not only achieves sub-micron or even nanometer-scale interconnect pitches, but also significantly reduces signal delay and power consumption, thereby enhancing chip bandwidth and capacity, and provides key support for the realization of high-performance chips. In the post-Moore era, hybrid bonding is regarded as a core development direction in advanced packaging, offering narrow-pitch, high-density, and miniaturized interconnect structures to meet the stringent performance requirements of emerging applications on chip performance. Hybrid bonding technology for high-density interconnects is systematically introduced, focusing on the novel metal passivation layer and other key materials as well as the core processes employed. The current status and development trend of hybrid bonding technology in the field of high-bandwidth memory is discussed in depth, aiming to provide valuable insights and guidance for the continuous innovation and evolution of advanced packaging technologies.

Key words: hybrid bonding, high-density interconnect, 3D integration, high-band width memory

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