2.5D封装关键技术的研究进展

doi:10.16257/j.cnki.1681-1070.2025.0111

摘要/Abstract

摘要： 随着摩尔定律指引下的晶体管微缩逼近物理极限，先进封装技术通过系统微型化与异构集成，成为突破芯片性能瓶颈的关键路径。作为先进封装的核心分支，2.5D封装通过硅/玻璃中介层实现高密度互连与多芯片异构集成，兼具高带宽、低延迟和小型化优势，广泛应用于人工智能、高性能计算及移动电子领域。系统阐述了2.5D封装的核心结构(如CoWoS、EMIB和I-Cube)及其技术特征，重点剖析了Chiplet模块化设计、硅通孔(TSV)工艺优化、微凸点可靠性提升、铜-铜直接键合界面工程以及再布线层多物理场协同设计等关键技术的最新进展。未来研究需聚焦低成本玻璃基板、原子层沉积技术抑制界面氧化以及多物理场协同设计等方面，以突破良率和散热瓶颈，推动2.5D封装在后摩尔时代高算力场景中的广泛应用。

关键词: 2.5D封装, 再布线层, 微凸点, 硅通孔, 铜-铜直接键合

Abstract: As Moore’s Law approaches its physical limits in transistor scaling, advanced packaging technologies have emerged as pivotal pathways to overcome performance bottlenecks through system miniaturization and heterogeneous integration. As a critical branch of advanced packaging, 2.5D packaging enables high-density interconnects and multi-chip heterogeneous integration via silicon/glass interposers, offering advantages in high bandwidth, low latency, and compact form factors, which is widely adopted in artificial intelligence, high-performance computing, and mobile electronics. The core architectures of 2.5D packaging (e.g., CoWoS, EMIB, and I-Cube) and their technical characteristics are systematically described, with a focused analysis of the latest advancements in key technologies, such as modular design of chiplet, process optimization of through-silicon via (TSV), reliability enhancement of microbumps, interface engineering of Cu-Cu direct bonding, and multi-physics co-design of redistribution layers. Future research should focus on low-cost glass substrates, atomic-layer-deposition-enabled interface oxidation suppression, and multi-physics co-design methodologies to overcome yield and thermal management bottlenecks, thereby accelerating the adoption of 2.5D packaging in high-performance computing scenarios within the post-Moore era.

Key words: 2.5D packaging, redistribution layer, microbump, through-silicon via, Cu-Cu direct bonding

中图分类号:

TN305.94

马千里, 马永辉, 钟诚, 李晓, 廉重, 刘志权. 2.5D封装关键技术的研究进展[J]. 电子与封装, 2025, 25(5): 050107 .

MA Qianli, MA Yonghui, ZHONG Cheng, LI Xiao, LIAN Zhong, LIU Zhiquan. Research Progress on Key Technologies of 2.5D Packaging[J]. Electronics & Packaging, 2025, 25(5): 050107 .

参考文献

[1] 曹立强, 侯峰泽, 王启东, 等. 先进封装技术的发展与机遇[J]. 前瞻科技, 2022, 1(3): 101-114.
[2] 费久斌. 异构集成2.5D封装结构界面剥离及C4焊点热疲劳行为的有限元模拟研究[D]. 广州：华南理工大学，2021.
[3] ARNAUD L, KARAM C, BRESSON N, et al. Three-dimensional hybrid bonding integration challenges and solutions toward multi-wafer stacking[J]. MRS Communications, 2020, 10(4): 549-557.
[4] 褚正浩, 张书强, 候明刚. 2.5D/3D芯片-封装-系统协同仿真技术研究[J]. 电子与封装, 2021, 21(10): 100103.
[5] LIU Y, YAO C, SUN F L, et al. Numerical simulation of reliability of 2.5D/3D package interconnect structure under temperature cyclic load[J]. Microelectronics Reliability, 2021, 125: 114343.
[6] KABIR M A, PETRANOVIC D, PENG Y R. Coupling extraction and optimization for heterogeneous 2.5D chiplet-package co-design[C]// Proceedings of the 39th International Conference on Computer-Aided Design, Virtual, 2020: 1-8.
[7] KABIR M A. Design, extraction, and optimization tool flows and methodologies for homogeneous and heterogeneous multi-chip 2.5D systems[M]. Fayetteville: University of Arkansas, 2021.
[8] ZHAO J, CHEN Z H, QIN F, et al. Development of high performance 2.5D packaging using glass interposer with through glass vias[J]. Journal of Materials Science: Materials in Electronics, 2023, 34(25): 1790.
[9] VIDEOCARD Z. AMD Fiji is the largest GPU ever made by AMD[EB/OL]. (2015-06-17)/[2025-03-07]. https://videocardz.com/56614/amd-fiji-is-the-largest-gpu-ever-made-by-amd.
[10] TSMC. CoWoS?[EB/OL]. [2025-03-07] https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/
cowos.htm.
[11] 邓运凯. 集成电路芯片扇出型板级封装工艺翘曲及湿气渗入的可靠性研究[D]. 广州：华南理工大学, 2025.
[12] Xilinx与台积公司宣布全线量产采用CoWoS技术的28 nm all programmable 3D IC系列[J]. 今日电子, 2013(11): 49.
[13] 袁渊, 张志模, 朱媛, 等. 基于硅桥芯片互连的芯粒集成技术研究进展[J]. 微电子学, 2024, 54(2): 255-263.
[14] MAHAJAN R, SANKMAN R, PATEL N, et al. Embedded multi-die interconnect bridge (EMIB): a high density, high bandwidth packaging interconnect[C]// 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, 2016: 557-565.
[15]三星半导体. 三星电子宣布推出面向高性能应用的下一代2.5D集成解决方案“I-Cube4”[EB/OL]. (2021-05-21)[2025-03-07]https://semiconductor.samsung.cn/news-events/news/samsung-electronics-announces-
availability-of-its-next-generation-2-5d-integration-solution-i-cube4-for-high-performance-application/.
[16] 张中, 乔新宇, 龙欣江, 等. 2.5D Chiplet封装结构的热应力研究[J]. 传感技术学报, 2023, 36(7): 1024-1031.
[17] 李乐琪, 刘新阳, 庞健. Chiplet关键技术与挑战[J]. 中兴通讯技术, 2022, 28(5): 57-62.
[18] YANG Y L, WANG Y, YI T Y, et al. A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration[J]. Integration, 2024, 96: 102170.
[19] 周刚, 曹中复. 用于2.5D封装技术的微凸点和硅通孔工艺[J]. 微处理机, 2017, 38(2): 15-18.
[20] 阳柄贤. 三维芯片堆叠TSV结构微凸点互连与铜异构互连力学可靠性的模拟研究[D]. 广州: 华南理工大学, 2022.
[21] AMKOR. 2.5D/3D TSV高性能和功能性解决方案[EB/OL]. [2025-03-07] https://amkor.com/cn/technology/25d-3d-tsv/.
[22] MA Y, ROSHANGHIAS A, BINDER A. A comparative study on direct Cu-Cu bonding methodologies for copper pillar bumped flip-chips[J]. Journal of Materials Science: Materials in Electronics, 2018, 29(11): 9347-9353.
[23] 高丽茵, 李财富, 刘志权, 等. 先进电子封装中焊点可靠性的研究进展[J]. 机械工程学报, 2022, 58(2): 185-202.
[24] KIM M J, LEE S H, SUK K L, et al. Novel 2.5D RDL interposer packaging: a key enabler for the new era of heterogenous chip integration[C]// 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2021: 321-326.
[25] MANZ. 面板级封装RDL制程设备解决方案[EB/OL]. [2025-03-07] https://www.manz.com/ecomaXL/files/2024_FOPLP_Flyer_TC_read.pdf.
[26] ZHANG X, LIN J K, WICKRAMANAYAKA S, et al. Heterogeneous 2.5D integration on through silicon interposer[J]. Applied physics reviews, 2015, 2(2): 1-58.
[27] NAM S, KANG J, LEE I, et al. Investigation on package warpage and reliability of the large size 2.5D molded interposer on substrate (MIoS) package[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2022: 643-647.
[28] LAN J S, WU M L. Simulation of micro-bump interconnections failure analysis for 2.5D IC packaging[C]// 2016 17th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), Montpellier, France, 2016.
[29] LEE C C, LIN P T. Reliability-based design guidance of three-dimensional integrated circuits packaging using thermal compression bonding and dummy Cu/Ni/SnAg microbumps[J]. Journal of Electronic Packaging, 2014, 136(3): 031006.
[30] MURAI K, ONOZEKI H, KANG D, et al. Study of Fabrication and Reliability for the extremely large 2.5D advanced Package[C]// 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2023.
[31] 孙戈辉, 吴志军, 王茉. 基于Weibull分布2.5D封装热疲劳可靠性评估[J]. 信息技术与标准化, 2021(8): 63-66.
[32] 吕晓瑞, 刘建松, 黄颖卓, 等. 基于热测试芯片的2.5D封装热阻测试技术研究[J]. 电子与封装, 2023, 23(4): 040202.
[33] SHAO S, NIU Y L, WANG J, et al. Design guideline on board-level thermomechanical reliability of 2.5D package[J]. Microelectronics Reliability, 2020, 111: 113701.
[34] YIN W J, LAI W H, LU Y X, et al. Mechanical and thermal characterization analysis of chip-last fan-out chip on substrate[C]// 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC), San Diego, CA, USA, 2022: 1711-1719.
[35] WU X D, WANG Z Z, MA S L, et al. An RDL modeling and thermo-mechanical simulation method of 2.5D/3D advanced package considering the layout impact based on machine learning[J]. Micromachines, 2023, 14(8): 1531.
[36] GAO N Y, CAO Y Y, ZHU Y, et al. Imitation chip design based on TSV 2.5D package[C]// 2015 16th International Conference on Electronic Packaging Technology (ICEPT), Changsha, China, 2015: 122-124.

中国半导体行业协会封装分会会刊

中国电子学会电子制造与封装技术分会会刊