中国电子学会电子制造与封装技术分会会刊

中国半导体行业协会封测分会会刊

无锡市集成电路学会会刊

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电子与封装

• 封装、组装与测试 •    下一篇

3D封装焊点的可靠性分析

李英豪   

  1. 中稀(凉山)磁性材料有限公司,四川 冕宁  615601
  • 收稿日期:2026-06-18 修回日期:2026-07-08 出版日期:2026-07-10 发布日期:2026-07-10
  • 通讯作者: 李英豪

Reliability Analysis of Solder Joints in 3D Packaging

LI Yinghao   

  1. Zhongxi (Liangshan) Magnetic Materials Co., Ltd., Mianning 615601, China
  • Received:2026-06-18 Revised:2026-07-08 Online:2026-07-10 Published:2026-07-10

摘要: 在电子封装技术持续演化推进的背景下,3D Fabric-SoIC、InFo、X-Cube、Chiplet、EMIB、Foveros等3D-IC先进异构集成技术达成了WtW(Wafer to Wafer)、WtD(Wafer to Die)、SoC (System on Chip)晶圆级集成(WLP)。研究围绕2.5D/3D封装技术对焊点性能的新要求,采用Ansys有限元分析软件,参照MIL‑STD‑883标准建立热循环载荷(-55~125 ℃),对三种封装模型的焊点列阵进行了求解,探究了热循环对三种不同集成方式封装体的焊点可靠性影响,并针对封装体应力的冷热循环过程进行了分析。结果表明:硅通孔(TSV)结构的简单堆叠方式使得焊点最大应力位于拐角与Cu柱接触处,底层焊点为潜在危险区;WOB(Wire on Bump)结构因双芯片层增强刚度,底层焊点应力较TSV显著降低,但第二层内部焊点拐角因钎料膏全接触模式而成为应力集中点;重布线层(RDL)结构受重布线层热变形影响显著,应力最大值先增后减,应力集中位置偏离常规拐角规律,向中心偏移。研究为电子封装领域焊点材料的优化及可靠性提升提供了参考,并提出了规避焊点失效的结构设计建议。

关键词: 有限元分析, 异构集成, 可靠性, 热循环

Abstract: Against the backdrop of continuous evolution in electronic packaging technologies, advanced 3D‑IC heterogeneous integration technologies such as 3D Fabric‑SoIC, InFO, X‑Cube, Chiplet, EMIB, and Foveros have enabled wafer‑level packaging (WLP) and chip‑level integration schemes including WtW (wafer‑to‑wafer), WtD (wafer‑to‑die), and SoC (system‑on‑chip). This study focuses on the new requirements for solder joint performance imposed by 2.5D/3D packaging technologies. Using Ansys finite element analysis software and following the MIL‑STD‑883 standard, a thermal cycling load (-55 ℃ to 125  ℃) was established, and the solder joint arrays of three package models were solved. The effects of thermal cycling on the solder joint reliability of three different integration schemes were investigated, and the stress evolution during the heating and cooling cycles was analyzed. The results indicate that in the through silicon via (TSV) structure, the maximum stress occurs at the corner in contact with the Cu pillar, with the bottom‑layer solder joints being the potential risk area. In the WOB (wire on bump) structure, the double‑chip layer enhances stiffness, significantly reducing the stress of the bottom‑layer solder joints compared to TSV; however, the inner solder joints at the corners of the second layer become stress concentration points due to the full‑contact solder paste mode. In the RDL (redistribution layer) structure, the stress distribution is significantly affected by thermal deformation of the redistribution layer, with the maximum stress first increasing and then decreasing, and the stress concentration locations deviating from the conventional corner rule and shifting toward the center. This study provides a reference for the optimization of solder joint materials and reliability improvement in electronic packaging, and proposes structural design suggestions to avoid solder joint failure.

Key words: finite element analysis, heterogeneous integration, reliability, thermal cycling